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| ? semiconductor components industries, llc, 2010 april, 2010 ? rev. 0 1 publication order number: NCV7729/d NCV7729 8a h-bridge driver the NCV7729 is an intelligent, fully protected h ? bridge driver designed specifically for control of dc and stepper motors in safety critical applications under automotive/industrial environment. features ? operating v s battery supply voltage 5 v to 28 v ? operating v cc supply voltage 3.0 to 5.5 v ? 18 v survivability on v cc and all logic i/o pins ? typical r ds(on) = 150 m , r ds(max) = 300 m (150 c) ? continuous dc load current 5a (tc < 100 c) ? selectable output current limitation (2.5 a to 9.6 a) ? output switching frequency up to 30 khz ? monitoring of all supply voltages, safe power ? up state ? loss of gnd detection ? short ? circuit protection and thermal shutdown ? full diagnosis capability for open load, short to gnd/vs and shorted load conditions ? spi interface for configuration and diagnosis ? undervoltage lockout ? regulated charge pump for optimized emi behavior ? this is a pb ? free device ? ncv prefix for automotive and other applications requiring site and change controls typical applications ? automotive ? electronic throttle control (etc) ? variable intake geometry ? exhaust gas recirculation ? variable swirl ? blow ? off flap ? industrial device package shipping ? ordering information NCV7729bppr2g psop ? 20 (pb ? free) 750 / tape & reel psop ? 20 case 525ab marking diagram http://onsemi.com NCV7729bg awlyywwg 110 11 20 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
NCV7729 http://onsemi.com 2 out1 out2 core functions biasing and supply regulated chargepump output protection and diagnostics vcc chp vs gnd control logic driver & gate control 16bit spi ? i/f dgnd agnd gnd loss detection 10,11 4 5,16 12 20 1 14,15 6,7 3 19 13 18 17 2 9 8 so si sclk csb in1 in2 en dis/sf figure 1. block diagram NCV7729 http://onsemi.com 3 m c buf 22 nf main c supervisor c 5v / 3.3v reg2 5v / 3.3v reg1 100nf 100 f reverse battery & transient protection vbat vbat out1 out2 core functions biasing and supply regulated chargepump vcc chp vs gnd control logic ddriver & gate control 16bit spi ? i/f dgnd agnd gnd loss detection 10,11 4 5,16 12 20 1 14,15 6,7 3 19 13 18 17 2 9 8 so si sclk csb in1 in2 en dis/sf figure 2. etc application diagram output protection and diagnostics NCV7729 http://onsemi.com 4 package pin description pin# symbol description 1 agnd analog ground; device substrate. 2 sclk serial clock. clock input for spi communication (internal pullup to v cc ) 3 in1 control input 1 (internal pullup to v cc ) 4 chp charge pump in/output 5 vs supply voltage; must be connected to pin 16 externally 6 out1 output1; must be connected to pin 7 externally 7 out1 output1; must be connected to pin 6 externally 8 so serial output. 16 bit spi communications output. 9 si serial input. 16 bit spi communications input (internal pullup to v cc ) 10 gnd power ground. 11 gnd power ground. 12 vcc power supply for logic 13 en enable input (internal pulldown to agnd) 14 out2 output2; connect to pin 15 externally 15 out2 output2; connect to pin 14 externally 16 vs supply voltage; must be connected to pin 5 externally 17 csb chip select bar input. active low spi port operation (internal pullup to v cc ) 18 dis/sf disable input / status flag output (open drain w/ internal pullup to v cc ) 19 in2 control input 2 (pullup to v cc ) 20 dgnd digital ground. heat slug internally connected to agnd; device substrate agnd gnd dgnd gnd sclk in1 chp vs out1 out1 so si in2 dis/sf csb vs out2 out2 en vcc heat slug 1 figure 3. package pinout (top view) NCV7729 http://onsemi.com 5 maximum ratings (voltages are with respect to device substrate.) rating value unit battery supply and power outputs (vs, outx) (dc) (ac), t < 500 ms ? 1 to 40 ? 2 v digital supply (v cc ), logic input/output pins (en, dis/sf, inx, csb,sclk, so, si) ? 0.5 to 18 v charge pump supply, relative to vs v(chp) ? v(vs) 16 v operating junction temperature continuous t < 1 s ? 40 to 150 175 c storage temperature range ? 65 to 150 c peak reflow soldering temperature: pb ? free ? 60 to 150 seconds at 217 c (note 1) 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for additional information, see or download on semiconductor?s soldering and mounting techniques reference manual, solderrm/d , and application note and8003/d. attributes characteristic value unit electrostatic discharge, human body model (mil std 883d) all pins battery / output pins (vs, outx) (note 3) 2 8 kv electrostatic discharge, cdm 800 v moisture sensitivity level (note 2) msl 1 ? thermal resistances junction ? to ? ambient (copper area, thickness) theta ja ( 100 mm2, 2 oz ) (note 4) theta ja ( 300 mm2, 2 oz ) (note 4) theta ja ( 600 mm2, 2 oz ) (note 4) psi j ? board solder pad 78 47 36 1.5 c/w package thermal time constant 1 sec 2. for additional information, see or downl oad on semiconductor?s soldering and mounting techniques reference manual, solderrm/d, and application note and8003/d. 3. vs pins (pin 5, 16) connected together; all gnd pins (pin 1, 10, 11, 20) connected together. 4. thermal estimates are based on mounting the package on a 30 x 70 x 1.5 mm fr4 substrate. copper areas include traces and mounting area of the device. 1 oz is equivalent to 0.035 mm thick copper. t est/simulation is based on jedec jesd51.1, jesd51.2, and jesd51.3 standards still air chamber boundary conditions steady state thermal performance. recommended operating conditions symbol parameter min max unit vccop digital supply input voltage (v cc ) 3 5.5 v vsop battery supply input voltage (v s ) 5 28 v fophi foplo inx pwm frequency (c buf = 22 nf) charge pump in full power mode charge pump in reduced power mode ? 30 4 khz t j junction temperature ? 40 150 c t jac junction temperature ? transient ( t < 1s) 175 c NCV7729 http://onsemi.com 6 electrical characteristics ( ? 40 c < t j < 150 c, 5 v < v s < 28 v, 3 v < v cc < 5.5 v, en = v cc , dis/sf = gnd, c buf = 22 nf, unless otherwise specified) (note 5) characteristic symbol conditions min typ max unit power supplies v s supply current ivsop,pwm f pwm = 20 khz, i out = 0 a ? ? 30 ma ivsop,dc f pwm = 0, i out = 0 a ? ? 5.5 ma ivsdiag dis/sf = v cc , en = 0, sclk = 0, vs = 13.2 v config.enx = 1 out1 tied to out2 ? ? 6.0 ma ivsdis dis/sf = v cc , en = 0, sclk = 0, v s = 13.2 v config.enx = 0 0 v cc 5.5v t a 85 c; (note 6) ? ? 5.0 a v cc supply current ivccop csb = v cc , outputs enabled ? ? 2.0 ma v cc undervoltage lockout vccporon power ? on reset, rising 2.5 ? 3.0 v v cc por hysteresis vccporhy 0.1 ? ? v v cc overvoltage lockout vccov 5.5 ? ? v v s undervoltage lockout vsporoff switch ? off threshold, falling; (note 7) 3.6 4.4 5.0 v vsporon switch ? on threshold, rising 3.8 4.6 5.2 v v s por hysteresis vsporhy 0.1 ? 0.5 v power supply lockout delay pordly v cc , v s , or chp ? 20 50 s loss of ground lockout threshold g dif |v(agnd) ? v(dgnd)| ? ? 300 mv c buf = 22 nf, f pwm = 30 khz, chp full power mode chp regulation voltage vchp v(chp) ? v(vs) ? 10 13 v chp undervoltage lockout vchplv v(chp) ? v(vs) falling 4.5 ? 6 v chp undervoltage hysteresis vchphy 100 ? 400 mv chp output current limitation ilimchp v(chp) = 0 v ? ? 30 ma chp allowable external leakage ichplkg v(chp) ? v(vs), v s = 13.2 v, ichplkg = ? 150 a 8 ? ? v chp power on delay time v cc or v s por release until outx active t dact v(chp) > vchplv ? ? 1.0 ms power outputs ? dc characteristics output transistor on resistance ronoutx v s > 5 v, i out = 3 a ? 150 300 m ronoutxgm v s > 5 v, i out = 3 a, t j = ? 30 c ? ? 135 m ls current limit switch ? off threshold ilimlsx config.ocx = ic4 config.ocx = ic3 (default) config.ocx = ic2 config.ocx = ic1 8.0 5.4 4.4 2.0 9.6 6.6 5.5 2.5 11.1 7.8 6.6 3.0 a 5. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 6. the load must be connected between out1 and out 2 to achieve the low ? quiescent current standby mode. 7. vs must first exceed the vsporon switch ? on threshold for operation down to vsporoff. 8. the isdlsx and isdhsx thresholds are unaffected during temperature dependant current limit reduction. 9. no production test. 10. latency time between overcurrent or overtemp shutdown to reactivation of output stage via ena or dis/sf. 11. minimum latency between successive frames. 12. minimum hold time after ena h l or dis/sf l h. NCV7729 http://onsemi.com 7 electrical characteristics ( ? 40 c < t j < 150 c, 5 v < v s < 28 v, 3 v < v cc < 5.5 v, en = v cc , dis/sf = gnd, c buf = 22 nf, unless otherwise specified) (note 5) characteristic unit max typ min conditions symbol power outputs ? dc characteristics ls current limit vs. overcurrent tracking itrackls isdlsx ? ilimlsx 2 ? ? a ls overcurrent shutdown threshold isdlsx (note 8) config.ocx = ic4 config.ocx = ic3 (default) config.ocx = ic2 config.ocx = ic1 ? 8.5 ? ? 15.0 10.8 9.5 4.9 ? 13.0 ? ? a ls overcurrent shutdown tracking itracksdls ic4 ? ic3 ic3 ? ic2 ic3 ? ic1 3.0 0.8 4.1 4.3 1.2 5.5 5.6 1.6 6.9 a hs overcurrent shutdown threshold isdhsx (note 8) config.ocx = ic4 config.ocx = ic3 (default) config.ocx = ic2 config.ocx = ic1 ? ? 13.0 ? ? ? 15.0 ? 10.8 ? 9.5 ? 4.9 ? ? 8.5 ? ? a hs overcurrent shutdown tracking itracksdhs ic4 ? ic3 ic3 ? ic2 ic3 ? ic1 ? 5.6 ? 1.6 ? 6.9 ? 4.3 ? 1.2 ? 5.5 ? 3.0 ? 0.8 ? 4.1 a outx leakage current ileak, outx dis/sf = v cc , en = 0, sclk = 0, v s = 28 v config.enx = 0 v(outx) = 0 v ? 20 0 ? a start of temperature dependant current limit reduction tlim (note 9) 150 165 ? c thermal shutdown tsd (note 9) 175 ? ? c free ? wheel diode forward voltage vd outx off, i(out) = 3 a ? ? 2.0 v power outputs ? ac characteristics free ? wheel diode reverse recovery time trr (note 9) ? ? 100 ns disable delay time en or dis/sf outx tpddis ? ? 2.0 s output on delay ? inx outx tdon rl = 5 , v s = 15 v ? ? 4.0 s output off delay ? inx outx tdoff ? ? 4.0 s output switching time outxh outxl or outxl outxh tr,tf ? ? 4.0 s ls current limit blanking time tb v s = 13.2 v; l = 0.75 mh, r = 0.2 14 20.5 27 s ls current limit switch ? off time ta 16 23.5 31 s switch ? off to blanking tracking ta/tb 1.0 ? ? ? overcurrent fault filter time tdfault 1.0 2.0 ? s reactivation time after internal shutdown treact (notes 9 and 10) ? ? 200 s open load diagnostics open load diagnostic threshold vth1 en=gnd or dis/sf=v cc config.enx = 1 1.25 ? 2 v vth2 1.25 ? 2 v diagnostic pullup current i(out1) v(vs) = 13.2 v, v(out1) = 2 v ? 2000 ? ? 1000 a 5. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 6. the load must be connected between out1 and out 2 to achieve the low ? quiescent current standby mode. 7. vs must first exceed the vsporon switch ? on threshold for operation down to vsporoff. 8. the isdlsx and isdhsx thresholds are unaffected during temperature dependant current limit reduction. 9. no production test. 10. latency time between overcurrent or overtemp shutdown to reactivation of output stage via ena or dis/sf. 11. minimum latency between successive frames. 12. minimum hold time after ena h l or dis/sf l h. NCV7729 http://onsemi.com 8 electrical characteristics ( ? 40 c < t j < 150 c, 5 v < v s < 28 v, 3 v < v cc < 5.5 v, en = v cc , dis/sf = gnd, c buf = 22 nf, unless otherwise specified) (note 5) characteristic unit max typ min conditions symbol open load diagnostics diagnostic pulldown current i(out2) v(vs) = 13.2 v, v(out2) = 1.25 v 700 ? 1400 a diagnostic current tracking i(out1) / i(out2) 1.2 ? 1.8 ? open load detection delay time tddiag 40 ? 110 ms microcontroller interface ? dc characteristics digital input threshold si, sclk, csb, en, dis/sf, inx vthin ? 30 ? 70 ? %vcc input hysteresis vhyin 2 ? 10 %vcc input pulldown current en ipden v(en) = v cc ? ? 100 a input pullup current dis/sf, inx si, sclk, csb ipux v(pin) = 0 v ? 200 ? 50 ? 125 ? 20 ? a dis/sf output voltage output condition low vsfl config.dis/sf = 1, i(dis/sf) = 1 ma ? ? 0.4 v so ? output high vsoh i(so) = ? 1 ma, v cc = 5.0 v v cc ? 0.5 ? ? v so ? output low vsol i(so) = 1.6 ma ? ? 0.4 v so tristate leakage ilso csb = v cc ? 10 ? 10 a microcontroller interface ? ac characteristics (v cc = 5 v) input capacitance si, sclk, csb, en, dis/sf, inx cinx (note 9) ? ? 20 pf so tristate capacitance cso (note 9) ? ? 35 pf sclk frequency ? ? 5 mhz sclk clock period 200 ? ? ns sclk high time figure 4 #1 85 ? ? ns sclk low time figure 4 #2 85 ? ? ns sclk setup time figure 4 #3,4 85 ? ? ns si setup time figure 4 #11 50 ? ? ns si hold time figure 4 #12 50 ? ? ns csb setup time figure 4 #5,6 100 ? ? ns csb high time figure 4 #7 (note 11) 200 ? ? ns so rise time cload = 40 pf ? ? 25 ns so fall time cload = 40 pf ? ? 25 ns 5. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 6. the load must be connected between out1 and out 2 to achieve the low ? quiescent current standby mode. 7. vs must first exceed the vsporon switch ? on threshold for operation down to vsporoff. 8. the isdlsx and isdhsx thresholds are unaffected during temperature dependant current limit reduction. 9. no production test. 10. latency time between overcurrent or overtemp shutdown to reactivation of output stage via ena or dis/sf. 11. minimum latency between successive frames. 12. minimum hold time after ena h l or dis/sf l h. NCV7729 http://onsemi.com 9 electrical characteristics ( ? 40 c < t j < 150 c, 5 v < v s < 28 v, 3 v < v cc < 5.5 v, en = v cc , dis/sf = gnd, c buf = 22 nf, unless otherwise specified) (note 5) characteristic unit max typ min conditions symbol microcontroller interface ? ac characteristics (v cc = 5 v) so valid time figure 4 #10 cload = 40 pf; (note 9) ? ? 40 ns cload = 200 pf; (note 9) ? ? 150 ns en or dis/sf hold time en = l or dis/sf = h (note 12) 2.0 ? ? s 5. min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. 6. the load must be connected between out1 and out 2 to achieve the low ? quiescent current standby mode. 7. vs must first exceed the vsporon switch ? on threshold for operation down to vsporoff. 8. the isdlsx and isdhsx thresholds are unaffected during temperature dependant current limit reduction. 9. no production test. 10. latency time between overcurrent or overtemp shutdown to reactivation of output stage via ena or dis/sf. 11. minimum latency between successive frames. 12. minimum hold time after ena h l or dis/sf l h. 10 si csb sclk sclk so 11 12 3 1 2 5 4 7 6 figure 4. spi timing parameters NCV7729 http://onsemi.com 10 detailed operating description bridge control inputs the integrated switches can be controlled by input signals (inx) as well as via the spi interface. mode selection is performed via the spi configuration register. the device provides two enable inputs: en = active high and dis/sf = active low. besides the two direct enable inputs en and dis/sf, the device provides two spi ? controllable bits in the configuration register (config.enx) to support a low ? quiescent current standby mode or advanced error handling (e.g. channel deactivation). the default setting for dis/sf is to operate as an enable input. by setting bit config.sfmode in the config register (spi command wr_config), the functionality of dis/sf can be altered to operate as an open ? drain status flag output. the config register can be accessed via the spi port independently of the setting at dis/sf. all control inputs provide internal pullup (in1, in2, dis/sf) or pulldown (en) to ensure defined functionality in case of open pin conditions. bridge control logic is shown in figure 5 and table 1 demonstrates all operational modes. table 1. h ? bridge operational modes operational mode en (note 13) dis/sf in (note 14) in1 (note 16) in2 (note 16) out1 out2 spi dis/sf out (note 15) forward h l h l h l see spi diagnostic description h reverse h l l h l h h free ? wheeling low h l l l l l h free ? wheeling high h l h h h h h disable via dis/sf (note 14) x h x x z z ? disable via en l x x x z z l en disconnected l x x x z z l dis/sf disconnected x h x x z z x in1 disconnected h l h x h x h in2 disconnected h l x h x h h current limitation active h l x x (note 17) (note 17) h under voltage (v s , chp) h l x x z z l overtemp shutdown h l x x z z l overcurrent shutdown h l x x z z l v cc under/over voltage x x x x z z h 13. en pulled down by internal current ipden. 14. dis/sf configured as enable input (config.sfmode = 0, default setting); pulled up by internal current ipux. 15. dis/sf configured as status flag output (config.sfmode= 1); pulled up by internal current ipux or external resistor. 16. device outputs enabled in config register (config.en1 = 1, config.en2 = 1, default setting); pulled up by internal current i pux. 17. affected output pulsing. see output protection description. NCV7729 http://onsemi.com 11 outxh outxl h = hs driver on h = ls driver on dis/sf spi: config.enx inx en r q s r vcc por vs undervoltage chp undervoltage vcc overtemp overcurrent spi: config.sfmode vcc reset_diag figure 5. bridge control logic bridge outputs the h ? bridge output is built up by four n ? channel power dmos devices (150 m typ, 300 m max @ 150 c). all transistors are protected against overcurrent and overtemperature conditions induced by short circuit conditions to gnd, v s , or across the load. positive and negative voltage transients that occur during switching events of inductive loads are clamped by integrated freewheeling diodes. an in tegrated regulated char gepump is provided to drive the gates of the high ? side dmos transistors. output protection to prevent device destruction in case of external fault conditions (outx shorted to gnd/vs or shorted load), all four output stages provide overcurrent shutdown and overtemperature shutdown functionality. low ? side current limitation and overcurrent shutdown to minimize the power dissipation in case of current limitation, a peak value control principle (figure 6) is integrated in each ls power stage. the current limitation level ic can be programmed by spi (config.ocx). the high ? side and low ? side i sd overcurrent levels are designed to track the programmed ic level. when the current limit ic is exceeded for a time tb, the affected low side stage is switched off, the corresponding high side stage is switched on for a fixed time ta, and the diagnostic register bit ?clim? will be latched to indicate peak current limitation active. the status flag (config.sfmode = 1) is not set in this case. if the overcurrent shutdown threshold i sd is exceeded for t > tdfault during the blanking time tb (figure 7), a short ? to ? vs condition is detected and the device transitions into the fault lockout state. all output transistors will be latched off, the status flag will be set and latched (config.sfmode = 1), and diagnostic register bits ?short circuit to v s ? will be latched to indicate the fault condition. high ? side overcurrent shutdown both hs transistors are protected against shorted outputs to gnd by an individual overcurrent shutdown. the high ? side and low ? side i sd overcurrent levels are designed to track the programmed ic level. if the overcurrent shutdown threshold i sd is exceeded for t > tdfault (figure 7), a short ? to ? gnd condition is detected and the device transitions into the fault lockout state. all output transistors will be latched off, the status flag will be set and latched (config.sfmode = 1), and diagnostic register bits ?short circuit to gnd? will be latched to indicate the fault condition. shorted load in case of a shorted load, both active hs and ls stages indicate an overcurrent condition. (ls: current limitation level exceeded, hs: overcurrent shutdown threshold level exceeded). all output transistors will be latched off, the status flag will be set and latched (config.sfmode = 1), and diagnostic register bits ?short circuit overload? will be latched to indicate the fault condition. NCV7729 http://onsemi.com 12 current limitation level (spi programmable) overcurrent shutdown level (hs,ls ? tracks i c ) ta tb iload t output enable t i sd ic figure 6. ls peak current limitation ls current limitation level (spi programmable) overcurrent shutdown level (hs,ls ? tracks i c ) tb iload t t i sd ic dis/sf (configured as output) t tdfault output enable figure 7. overcurrent shutdown (hs & ls) overtemperature the device is protected against excessive junction temperatures by integrated temperature sensors. in case of exceeding the overtemperature shutdown point tsd (175 c min), all output transistors will be latched off, the status flag will be set and latched (config.sfmode = 1), and diagnostic register bit ?ot? will be latched to indicate the fault condition. temperature ? dependent peak current reduction when the junction temperature is between tlim (165 c typ.) and tsd, the programmed peak current is reduced as shown in figure 8. the diagnostic register bit ?cred? will be latched to indicate peak current reduction active. the status flag (config.sfmode = 1) is not set in this case. the region of operation is indicated by rd_config register bits ?th1?and ?th0?. thx bits are cleared by a rising edge on en while dis/sf = 0 or a falling edge on dis/sf while en = 1, or by reading the diagnostic register via the rd_diag command. whenever the programmed i c level is reduced in the region between tlim and tsd, the reduced i c level is latched. the high ? side and low ? side i sd overcurrent levels are unaffected during temperature dependant current limit reduction. the originally programmed i c level is restored by a rising edge on en while dis/sf = 0 or a falling edge on dis/sf while en = 1, or by reading the diagnostic register via the rd_diag command. NCV7729 http://onsemi.com 13 ic4 ic3 ic1 ic2 ic tj( c ) tlim (default) spi prog ra mma ble preset value tsd r e s t r i c t e d a r e a th1,th0 = 1,1 (default) =1,0 =0,1 =0,0 figure 8. temperature ? dependent peak current reduction open load diagnostics while short to gnd/vs or shorted load fault conditions at the outputs will be detected in active mode , open load detection is performed in off ? mode. the open load diagnostic is activated by disabling the NCV7729?s power stages via the enable inputs en and dis/sf (config.sfmode = 0). to allow a low ? quiescent current mode, the diagnostic function can be deactivated via the spi config register (config.enx = 0). the device?s operating modes invoked via the enable inputs and the config.enx register bits are detailed in table 2. figure 9 shows the open load diagnostic scheme. the diagnostic is performed by applying two different currents to the outputs out1 and out2. the diagnostic result is determined by a simple comparison of both pin voltages to two separate reference voltages. the diagnostic results are shown in table 3. open load feedback signal vth1 vth2 iout2 gnd out1 out2 vs iout1 spi: config .sfmode en dis/sf internal rail spi: config .en1 spi: config .en2 agnd figure 9. open load detection NCV7729 http://onsemi.com 14 table 2. NCV7729 operating modes en dis/sf config.en1 config.en2 operating mode 0 x 0 x standby 0 x x 0 standby 0 x 1 1 open load diagnosis x 1 1 1 open load diagnosis 1 0 0 0 standby 1 0 1 1 normal operation (outputs active) table 3. open load diagnostics results failure mechanism v(out1) v(out2) diagnostic result load inserted >vth1 >vth2 no fault open load >vth1 NCV7729 http://onsemi.com 15 overvoltage is handled as a latched lockout condition, requiring re ? enable of the device by appropriate transitions on the en and dis/sf (config.sfmode = 0) enable inputs. diagnostic and status information is lost when v cc overvoltage occurs and it is required to re ? program the configuration register unless default settings are used. loss of ground failure loss of ground failure is detected when a difference in potential (g dif ) between the agnd and dgnd pins exists. in the event of ground loss failure, the device transitions into fault lockout state and the output stages are turned into hi ? z mode. loss of ground is handled as a latched lockout condition. diagnostic and status information is lost when loss of ground occurs. fault handling fault handling states are shown in figure 11. all overcurrent and overtemperature events cause a latched lockout of the output stages. v cc under/over voltage faults or loss of agnd or dgnd faults are handled as a latched lockout condition, requiring re ? enable of the device. the device can be returned to normal operating mode by either a rising edge on en while dis/sf = 0, or a falling edge on dis/sf while en = 1. undervoltage on v s or chp result in a non ? latched lockout event (outx = z until the supply voltage returns into operating range). in status flag mode (config.sfmode = 1), dis/sf will be set low when en goes h l and is reset when en goes l h. the status flag is set and latched when a fault condition is detected that causes transition to a latched lockout state. in the case of v s or chp undervoltage the status flag is set, but is reset when the supply voltage returns into operating range (see table 1). all fault conditions (except v cc or loss of ground faults) that lead to a fault lockout state are stored in the diagnostic register in a latched manner. a fault lockout state also causes the configuration register ?lock? bit to be set (rd_config:b4 = 1). in the case of vs or chp undervoltage the configuration ?lock? bit is not set and diagnostic register data is not latched (see note 18 on page 20). diagnostic and configuration register data will persist until the microcontroller performs an action to reset the device or register. the device status can be read by accessing the diagnostic register via the rd_diag or wr_config spi commands. the state of the ?lock? bit can be accessed via the rd_config command. the diagnostic register can be reset by: ? a read access to the register via spi command rd_diag (reset occurs on the rising edge of csb if valid spi frame) ? a rising edge on en while dis/sf = 0 or a falling edge on dis/sf while en = 1 ? vcc under/over voltage or loss of agnd or dgnd accessing the diagnostic register via the wr_config command or disabling the outputs via the config.enx bits does not reset the diagnostic register contents. the configuration register ?lock? bit can be reset by: ? a rising edge on en while dis/sf = 0 or a falling edge on dis/sf while en = 1 ? vcc under/over voltage or loss of agnd or dgnd at power ? up, default diagnostic register content is b[7:0] = 0xf0 and configuration register ?lock? bit b4 = 1. normal operation fault lockout vccov / vccuv loss of agnd or dgnd vs / chp undervoltage outx = z dis/sf = l (if configured as output ) outx = z outx = z dis/sf = l (if configured as output ) v(vs) < vsporoff v(vs) > vsporon output fault condition v(vcc) < vccporon or v(vcc) > vccov v(vcc) > vccporon outx controlled by: en, dis/sf, inx, spi:config. enx spi reset ? default settings power ? up figure 11. fault handling state diagram (shorted load, overcurrent, overtemp) or v(chp) ? v(vs) < vchply and v(chp) ? v(vs) > vchply device enable: en: l h dis/sf: h l NCV7729 http://onsemi.com 16 16 ? bit spi interface the 4 ? wire spi interface establishes a full duplex synchronous serial communication link between the NCV7729 and the application?s microcontroller. the NCV7729 always operates in slave mode whereas the controller provides the master function. the NCV7729 is accessed by the spi master by applying an active ? low slave select signal at csb. si is the data input, so the data output. the spi master provides the clock to the NCV7729 via the sclk input. the data output so is high impedance (tri ? state) when csb is high. the uppermost two bits of the si data frame are used as a chip id to allow extended addressing. the chip id is fixed to 00 for the NCV7729. to avoid a bus conflict, the so output is held in tri ? state until the id bits have been successfully received and decoded. if the id does not match the fixed NCV7729 id, the entire frame is ignored and so remains tri ? state. the extended addressing feature therefore does not allow spi daisy ? chaining through the NCV7729. spi frame format the general format of the NCV7729?s spi frame is shown in figure 12. both 16 ? bit input and 14 ? bit output data are msb first. the device supports in ? frame response to minimize the amount of cpu overhead for communication. the response data is transmitted within the same access cycle immediately after decoding the id and command bits. each spi access is checked for consistency such that input data written to internal registers (a write access is executed) only when all of the following occur: ? recognition of a valid chip id ? a valid number of sclk cycles (16) ? recognition of a valid command a transmission error is indicated by setting a flag bit (tf) in the case of an invalid number of sclk cycles or receipt of an invalid command. the tf bit can be checked by the microcontroller in the verification response following the frame in which transmission error occurred. the tf bit is reset after receipt of the next valid frame. data stored in the device?s configuration and diagnostic registers is unaf fected in the case of a transmission error. si so csb 16 ? bit write access write data (8) lsb msb lsb verification (6) msb lsb return data (8) lsb msb id(2) command (6) si so csb 16 ? bit read access don?t care (8) lsb msb lsb verification (6) msb lsb return data (8) lsb msb id(2) command (6) id=?00? id=?00? si so csb invalid address cycle id(2) don?t care (n) id <>?00? msb msb figure 12. general 16 ? bit spi frame format. NCV7729 http://onsemi.com 17 general spi timing the general spi timing shown in figure 13 is defined as follows for the NCV7729: ? the change at output so is forced by the rising edge of the sclk signal if a valid chip id is recognized; otherwise so remains tri ? state ? the si input signal is latched on the falling edge of the sclk signal ? the data received during a write access are written into the internal registers at the rising edge of the csb signal only when all of the following occur: ? a valid chip id is recognized ? exactly 16 sclk cycles were counted during csb = low ? a valid command is recognized csb sclk so 1 2 3 14 15 16 msb lsb 4 ? 13 si b15 b14 b13 b12 ? b3 b2 b1 b0 tri ? state b13 b2 b1 b0 b12 ? b3 figure 13. spi timing diagram NCV7729 http://onsemi.com 18 register and command structure overview prototype r/w command in id1 id0 cd5 cd4 cd3 cd2 cd1 cd0 data in [7:0] verification out z z 1 0 1 0 1 tf data out [7:0] bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wr_config w advanced feature control in 0 0 1 1 0 0 1 1 sf mode chp mode en2 en1 oc1 oc0 b1 b0 out z z 1 0 1 0 1 tf en ot cred clim d21 d20 d11 d10 rd_id r in 0 0 0 0 0 0 0 0 x x x x x x x x out z z 1 0 1 0 1 tf id[7:0] rd_rev r in 0 0 0 0 0 0 1 1 x x x x x x x x out z z 1 0 1 0 1 tf swr[3:0] msr[3:0] rd_config r in 0 0 1 0 1 0 0 0 x x x x x x x x out z z 1 0 1 0 1 tf sf mode chp mode enx lock oc1 oc0 th1 th0 rd_diag r in 0 0 0 0 1 0 0 1 x x x x x x x x out z z 1 0 1 0 1 tf en ot cred clim d21 d20 d11 d10 invalid id ? in < > ?00? x x x x x x x x x x x x x x out z z z z z z z z z z z z z z z z invalid cmd ? in 0 0 undefined x x x x x x x x out z z 1 0 1 0 1 tf 1 1 1 1 1 1 1 1 NCV7729 http://onsemi.com 19 detailed command description wr_config type: w function: programs the device configuration (valid spi frame detected). the wr_config returns the diagnostic register contents without resetting the register. the rd_diag command returns the diagnostic register contents and resets all latched data in the register. the wr_config register can only be changed when en = 0. command prototype: wr_config w advanced feature control in 0 0 1 1 0 0 1 1 sf mode chp mode en2 en1 oc1 oc0 b1 b0 out z z 1 0 1 0 1 tf en ot cred clim d21 d20 d11 d10 input parameter description: parameter description remarks b1 b0 reserved future use x x oc1 oc0 outx ls current limit 1 1 ic4 1 0 ic3 default 0 1 ic2 0 0 ic1 en1 out1 control 0 output 1 disabled 1 output 1 enabled default en2 out2 control 0 output 2 disabled 1 output 2 enabled default chpmode charge pump mode 0 full power mode default 1 reduced power mode sfmode dis/sf mode 0 dis/sf configured as enable input default 1 dis/sf configured as status flag output NCV7729 http://onsemi.com 20 output parameter description: parameter description remarks d21 d20 d11 d10 priority encoded diagnostic data (note 18) out2 status out1 status 1 1 0 0 shorted load data is latched x x 0 1 out1 short to v s data is latched x x 1 0 out1 short to gnd data is latched x x 1 1 out1 normal ? 0 0 1 1 open load data is latched 0 1 x x out2 short to vs data is latched 1 0 x x out2 short to gnd data is latched 1 1 x x out2 normal ? 0 0 0 0 v cc power ? on reset data is latched v s or chp undervoltage data is not latched clim outx ls current limit 0 outx ls current > icx data is latched 1 normal operation ? cred outx ls current limit reduction 0 t j > tlim data is latched 1 normal operation ? ot overtemperature 0 t j > tsd data is latched 1 normal operation ? en enable status (note 19) 0 outputs disabled data is not latched 1 outputs enabled ? tf transmission error flag 0 previous spi frame valid ? 1 transmission error detected data is latched b[13:9] verification = ?1 0 1 0 1? hard ? coded 18. the d[21:20] and d[11:10] diagnostic data are stored according to the following priority scheme: priority 1 (highest): vs or chp undervoltage priority 2: shorted load priority 3: short to gnd or vs priority 4: open load lower priority faults are overwritten by higher priority faults in the case of multiple faults. in the case of v s or chp undervoltage, overwritten fault data are restored after v s or chp returns into normal operating range. overwritten fault data can be retrieved via the wr_config command. resetting the diagnostic register via the enable inputs or the rd_diag command resets all latched data and overwritten fault data cannot be retrieved. at vcc power ? on reset d[21:10] = 0000. 19. the en bit reflects the enabled/disabled state of the outputs based on the state of the en or dis/sf input pins or the state of the wr_config bits en1or en2. NCV7729 http://onsemi.com 21 rd_id type: r function: returns the hard ? coded device identification (id). command prototype: rd_id r in 0 0 0 0 0 0 0 0 x x x x x x x x out z z 1 0 1 0 1 tf id[7:0] input parameter description: n/a output parameter description: parameter description remarks id[7:0] id = ?1 0 1 0 0 0 1 0? hard ? coded tf transmission error flag 0 previous spi frame valid ? 1 transmission error detected data is latched b[13:9] verification = ?1 0 1 0 1? hard ? coded rd_rev type: r function: returns the hard ? coded device revision counters. command prototype: rd_rev r in 0 0 0 0 0 0 1 1 x x x x x x x x out z z 1 0 1 0 1 tf swr[3:0] msr[3:0] input parameter description: n/a output parameter description: parameter description remarks msr[3:0] msr = ?0 0 0 1? hard ? coded swr[3:0] swr = ?0 0 0 0? hard ? coded tf transmission error flag 0 previous spi frame valid ? 1 transmission error detected data is latched b[13:9] verification = ?1 0 1 0 1? hard ? coded NCV7729 http://onsemi.com 22 rd_config type: r function: returns the device configuration parameters. command prototype: rd_config r in 0 0 1 0 1 0 0 0 x x x x x x x x out z z 1 0 1 0 1 tf sf mode chp mode enx lock oc1 oc0 th1 th0 input parameter description: n/a output parameter description: parameter description remarks th1 th0 state of temperature ? dependent current limit data is latched 1 1 t j < tlim default 1 0 tlim < t j < tsd see figure 8 0 1 tlim < t j < tsd 0 0 t j > tsd oc1 oc0 outx ls current limit via wr_config ocx 1 1 ic4 1 0 ic3 default 0 1 ic2 0 0 ic1 lock fault lockout data is latched 0 outputs enabled 1 output disabled default enx output control via wr_config enx (note 20) 0 outx disabled 1 out1 and out2 enabled default chpmode charge pump mode 0 full power mode default 1 reduced power mode sfmode dis/sf mode 0 dis/sf configured as enable input default 1 dis/sf configured as status flag output tf transmission error flag 0 previous spi frame valid ? 1 transmission error detected data is latched b[13:9] verification = ?1 0 1 0 1? hard ? coded 20. the enx bit reflects the enabled/disabled state of the outputs based on the state of the wr_config bits en1or en2. NCV7729 http://onsemi.com 23 rd_diag type: r function: returns the diagnostic register contents and resets the register (valid spi frame detected). the rd_diag command returns the diagnostic register contents and resets all latched data in the register. the wr_config command can be used to return the diagnostic register contents without resetting the register. command prototype: rd_diag r in 0 0 0 0 1 0 0 1 x x x x x x x x out z z 1 0 1 0 1 tf en ot cred clim d21 d20 d11 d10 input parameter description: n/a output parameter description: parameter description remarks d21 d20 d11 d10 priority encoded diagnostic data (note 18) out2 status out1 status 1 1 0 0 shorted load data is latched x x 0 1 out1 short to v s data is latched x x 1 0 out1 short to gnd data is latched x x 1 1 out1 normal ? 0 0 1 1 open load data is latched 0 1 x x out2 short to v s data is latched 1 0 x x out2 short to gnd data is latched 1 1 x x out2 normal ? 0 0 0 0 v cc power ? on reset data is latched v s or chp undervoltage data is not latched clim outx ls current limit 0 outx ls current > icx data is latched 1 normal operation ? cred outx ls current limit reduction 0 t j > tlim data is latched 1 normal operation ? ot overtemperature 0 t j > tsd data is latched 1 normal operation ? en enable status note 18 0 outputs disabled data is not latched 1 outputs enabled ? tf transmission error flag 0 previous spi frame valid ? 1 transmission error detected data is latched b[13:9] verification = ?1 0 1 0 1? hard ? coded NCV7729 http://onsemi.com 24 0.001 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) r(t) ( c/w) figure 14. transient thermal performance on 100 mm 2 2 oz. heat spreader 10% 5% 2% 20% 1% 50% duty cycle max psi ba single pulse 0.001 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse time (sec) r(t) ( c/w) figure 15. transient thermal performance on 600 mm 2 2 oz. heat spreader 10% 5% 2% 20% 1% 50% duty cycle max psi ba single pulse 0 20 40 60 80 100 120 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 ja ( c/w) time (sec) figure 16. transient thermal performance on various 2 oz. heat spreaders 50 mm 2 100 mm 2 150 mm 2 200 mm 2 300 mm 2 500 mm 2 NCV7729 http://onsemi.com 25 package dimensions psop ? 20 case 525ab ? 01 issue a dim min max millimeters a 3.00 3.40 a1 a2 2.90 3.10 d1 11.70 12.60 d2 0.90 1.10 e2 2.50 2.70 l 0.84 1.10 b 0.40 0.52 b1 0.40 0.49 c 0.23 0.32 c1 0.23 0.28 e 1.27 bsc h --- 1.10 0 8 d 15.90 bsc e gauge plane bottom view detail a x 45 e1 h 0.20 c 20 11 10 1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. datum plane h is located at the bottom of the lead and is coincident with the lead where it exits the body at the bottom of the parting line. 4. dimension d does not include mold flash, protrusions, or gate burrs. mold flash or gate burrs shall not exceed 0.15 per side. d is determined at datum h. 5. dimension e1 does not include interlead flash protrusion. interlead flash protrusion shall not exceed 0.15 per side. e1 is determined at datum h. 6. a visual identifier is located within the cross-hatched area. 7. these dimensions apply to the flat section of the lead between 0.10 and 0.25mm from the tip. 8. seating plane is defined by the lead tips only. 9. dimension d does not include tiebar protrusions. tiebar protrusions shall not exceed 0.15 per side. 10. datums a and b to be determined at datum h. e3 d1 ??? ??? section a ? a b c1 b1 c e3 6.40 7.20 b h e1 11.00 bsc pin 1 0.10 0.30 a3 0.00 0.10 l1 0.35 bsc 6 e 4 0.10 c ident area 5 d2 2x 9 2x 10 tips 4x (datum plane a) e/2 7 a a d seating e 7 3 plane b 20x a m 0.25 b c a2 c 10 detail b 0.10 c a1 a3 detail b l1 e2 2x detail a 9 b 8 e4 e4 2.70 2.90 13.95 14.45 mounting footprint* 14.66 1.27 1.33 20x 16.06 dimensions: millimeters 7.20 1 20x 0.62 12.60 pitch 2.90 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. NCV7729 http://onsemi.com 26 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCV7729/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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